mirror of https://gitee.com/bigwinds/arangodb
Updated matthias kretz's OptimizeForArchitecture
This commit is contained in:
Kaveh Vahedipour
parent
764615cc62
commit
8f4fdc6114
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@ -1,5 +1,23 @@
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# Determine the host CPU feature set and determine the best set of compiler
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# flags to enable all supported SIMD relevant features. Alternatively, the
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# target CPU can be explicitly selected (for generating more generic binaries
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# or for targeting a different system).
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# Compilers provide e.g. the -march=native flag to achieve a similar result.
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# This fails to address the need for building for a different microarchitecture
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# than the current host.
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# The script tries to deduce all settings from the model and family numbers of
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# the CPU instead of reading the CPUID flags from e.g. /proc/cpuinfo. This makes
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# the detection more independent from the CPUID code in the kernel (e.g. avx2 is
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# not listed on older kernels).
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#
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# Usage:
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# OptimizeForArchitecture()
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# If either of Vc_SSE_INTRINSICS_BROKEN, Vc_AVX_INTRINSICS_BROKEN,
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# Vc_AVX2_INTRINSICS_BROKEN is defined and set, the OptimizeForArchitecture
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# macro will consequently disable the relevant features via compiler flags.
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#=============================================================================
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# Copyright 2010-2013 Matthias Kretz <kretz@kde.org>
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# Copyright 2010-2015 Matthias Kretz <kretz@kde.org>
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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@ -7,15 +25,12 @@
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#
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# * Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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#
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# * Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# * The names of Kitware, Inc., the Insight Consortium, or the names of
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# any consortium members, or of any contributors, may not be used to
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# endorse or promote products derived from this software without
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# specific prior written permission.
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# * Neither the names of contributing organizations nor the
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# names of its contributors may be used to endorse or promote products
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# derived from this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS ``AS IS''
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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@ -31,7 +46,7 @@
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get_filename_component(_currentDir "${CMAKE_CURRENT_LIST_FILE}" PATH)
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include("${_currentDir}/AddCompilerFlag.cmake")
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include(CheckIncludeFile)
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include(CheckIncludeFileCXX)
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macro(_my_find _list _value _ret)
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list(FIND ${_list} "${_value}" _found)
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@ -70,47 +85,58 @@ macro(AutodetectHostArchitecture)
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endif(CMAKE_SYSTEM_NAME STREQUAL "Linux")
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if(_vendor_id STREQUAL "GenuineIntel")
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if(_cpu_family EQUAL 6)
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# Any recent Intel CPU except NetBurst
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if(_cpu_model EQUAL 70)
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set(TARGET_ARCHITECTURE "haswell")
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elseif(_cpu_model EQUAL 63)
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set(TARGET_ARCHITECTURE "haswell")
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elseif(_cpu_model EQUAL 62)
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set(TARGET_ARCHITECTURE "ivy-bridge")
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elseif(_cpu_model EQUAL 61)
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# taken from the Intel ORM
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# http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html
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# CPUID Signature Values of Of Recent Intel Microarchitectures
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# 4E 5E | Skylake microarchitecture
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# 3D 47 56 | Broadwell microarchitecture
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# 3C 45 46 3F | Haswell microarchitecture
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# 3A 3E | Ivy Bridge microarchitecture
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# 2A 2D | Sandy Bridge microarchitecture
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# 25 2C 2F | Intel microarchitecture Westmere
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# 1A 1E 1F 2E | Intel microarchitecture Nehalem
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# 17 1D | Enhanced Intel Core microarchitecture
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# 0F | Intel Core microarchitecture
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#
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# Values from the Intel SDE:
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# 5C | Goldmont
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# 5A | Silvermont
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# 57 | Knights Landing
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# 66 | Cannonlake
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# 55 | Skylake Server
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# 4E | Skylake Client
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# 3C | Broadwell (likely a bug in the SDE)
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# 3C | Haswell
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if(_cpu_model EQUAL 87)
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set(TARGET_ARCHITECTURE "knl") # Knights Landing
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elseif(_cpu_model EQUAL 92)
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set(TARGET_ARCHITECTURE "goldmont")
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elseif(_cpu_model EQUAL 90)
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set(TARGET_ARCHITECTURE "silvermont")
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elseif(_cpu_model EQUAL 102)
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set(TARGET_ARCHITECTURE "cannonlake")
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elseif(_cpu_model EQUAL 85) # 55
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set(TARGET_ARCHITECTURE "skylake-avx512")
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elseif(_cpu_model EQUAL 78 OR _cpu_model EQUAL 94) # 4E, 5E
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set(TARGET_ARCHITECTURE "skylake")
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elseif(_cpu_model EQUAL 61 OR _cpu_model EQUAL 71 OR _cpu_model EQUAL 86)
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set(TARGET_ARCHITECTURE "broadwell")
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elseif(_cpu_model EQUAL 60)
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elseif(_cpu_model EQUAL 60 OR _cpu_model EQUAL 69 OR _cpu_model EQUAL 70 OR _cpu_model EQUAL 63)
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set(TARGET_ARCHITECTURE "haswell")
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elseif(_cpu_model EQUAL 60)
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set(TARGET_ARCHITECTURE "haswell")
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elseif(_cpu_model EQUAL 58)
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elseif(_cpu_model EQUAL 58 OR _cpu_model EQUAL 62)
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set(TARGET_ARCHITECTURE "ivy-bridge")
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elseif(_cpu_model EQUAL 47) # Xeon E7 4860
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set(TARGET_ARCHITECTURE "westmere")
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elseif(_cpu_model EQUAL 46) # Xeon 7500 series
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set(TARGET_ARCHITECTURE "westmere")
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elseif(_cpu_model EQUAL 45) # Xeon TNG
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elseif(_cpu_model EQUAL 42 OR _cpu_model EQUAL 45)
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set(TARGET_ARCHITECTURE "sandy-bridge")
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elseif(_cpu_model EQUAL 44) # Xeon 5600 series
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elseif(_cpu_model EQUAL 37 OR _cpu_model EQUAL 44 OR _cpu_model EQUAL 47)
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set(TARGET_ARCHITECTURE "westmere")
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elseif(_cpu_model EQUAL 42) # Core TNG
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set(TARGET_ARCHITECTURE "sandy-bridge")
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elseif(_cpu_model EQUAL 37) # Core i7/i5/i3
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set(TARGET_ARCHITECTURE "westmere")
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elseif(_cpu_model EQUAL 31) # Core i7/i5
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set(TARGET_ARCHITECTURE "westmere")
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elseif(_cpu_model EQUAL 30) # Core i7/i5
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set(TARGET_ARCHITECTURE "westmere")
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elseif(_cpu_model EQUAL 29)
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set(TARGET_ARCHITECTURE "penryn")
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elseif(_cpu_model EQUAL 28)
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set(TARGET_ARCHITECTURE "atom")
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elseif(_cpu_model EQUAL 26)
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elseif(_cpu_model EQUAL 26 OR _cpu_model EQUAL 30 OR _cpu_model EQUAL 31 OR _cpu_model EQUAL 46)
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set(TARGET_ARCHITECTURE "nehalem")
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elseif(_cpu_model EQUAL 23)
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elseif(_cpu_model EQUAL 23 OR _cpu_model EQUAL 29)
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set(TARGET_ARCHITECTURE "penryn")
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elseif(_cpu_model EQUAL 15)
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set(TARGET_ARCHITECTURE "merom")
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elseif(_cpu_model EQUAL 28)
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set(TARGET_ARCHITECTURE "atom")
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elseif(_cpu_model EQUAL 14)
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set(TARGET_ARCHITECTURE "core")
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elseif(_cpu_model LESS 14)
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@ -152,7 +178,15 @@ macro(AutodetectHostArchitecture)
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endmacro()
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macro(OptimizeForArchitecture)
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set(TARGET_ARCHITECTURE "auto" CACHE STRING "CPU architecture to optimize for. Using an incorrect setting here can result in crashes of the resulting binary because of invalid instructions used.\nSetting the value to \"auto\" will try to optimize for the architecture where cmake is called.\nOther supported values are: \"none\", \"generic\", \"core\", \"merom\" (65nm Core2), \"penryn\" (45nm Core2), \"nehalem\", \"westmere\", \"sandy-bridge\", \"ivy-bridge\", \"haswell\", \"broadwell\", \"atom\", \"k8\", \"k8-sse3\", \"barcelona\", \"istanbul\", \"magny-cours\", \"bulldozer\", \"interlagos\", \"piledriver\", \"AMD 14h\", \"AMD 16h\".")
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set(TARGET_ARCHITECTURE "auto" CACHE STRING "CPU architecture to optimize for. \
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Using an incorrect setting here can result in crashes of the resulting binary because of invalid instructions used. \
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Setting the value to \"auto\" will try to optimize for the architecture where cmake is called. \
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Other supported values are: \"none\", \"generic\", \"core\", \"merom\" (65nm Core2), \
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\"penryn\" (45nm Core2), \"nehalem\", \"westmere\", \"sandy-bridge\", \"ivy-bridge\", \
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\"haswell\", \"broadwell\", \"skylake\", \"skylake-avx512\", \"cannonlake\", \"silvermont\", \
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\"goldmont\", \"knl\" (Knights Landing), \"atom\", \"k8\", \"k8-sse3\", \"barcelona\", \
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\"istanbul\", \"magny-cours\", \"bulldozer\", \"interlagos\", \"piledriver\", \
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\"AMD 14h\", \"AMD 16h\".")
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set(_force)
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if(NOT _last_target_arch STREQUAL "${TARGET_ARCHITECTURE}")
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message(STATUS "target changed from \"${_last_target_arch}\" to \"${TARGET_ARCHITECTURE}\"")
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@ -170,6 +204,58 @@ macro(OptimizeForArchitecture)
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message(STATUS "Detected CPU: ${TARGET_ARCHITECTURE}")
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endif(TARGET_ARCHITECTURE STREQUAL "auto")
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macro(_nehalem)
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list(APPEND _march_flag_list "nehalem")
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list(APPEND _march_flag_list "corei7")
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list(APPEND _march_flag_list "core2")
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list(APPEND _available_vector_units_list "sse" "sse2" "sse3" "ssse3" "sse4.1" "sse4.2")
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endmacro()
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macro(_westmere)
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list(APPEND _march_flag_list "westmere")
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_nehalem()
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endmacro()
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macro(_sandybridge)
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list(APPEND _march_flag_list "sandybridge")
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list(APPEND _march_flag_list "corei7-avx")
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_westmere()
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list(APPEND _available_vector_units_list "sse" "sse2" "sse3" "ssse3" "sse4.1" "sse4.2" "avx")
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endmacro()
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macro(_ivybridge)
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list(APPEND _march_flag_list "ivybridge")
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list(APPEND _march_flag_list "core-avx-i")
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_sandybridge()
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list(APPEND _available_vector_units_list "rdrnd" "f16c")
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endmacro()
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macro(_haswell)
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list(APPEND _march_flag_list "haswell")
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list(APPEND _march_flag_list "core-avx2")
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_ivybridge()
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list(APPEND _available_vector_units_list "avx2" "fma" "bmi" "bmi2")
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endmacro()
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macro(_broadwell)
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list(APPEND _march_flag_list "broadwell")
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_haswell()
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endmacro()
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macro(_skylake)
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list(APPEND _march_flag_list "skylake")
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_broadwell()
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endmacro()
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macro(_skylake_avx512)
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list(APPEND _march_flag_list "skylake-avx512")
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_skylake()
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list(APPEND _available_vector_units_list "avx512f" "avx512cd" "avx512dq" "avx512bw" "avx512vl")
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endmacro()
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macro(_cannonlake)
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list(APPEND _march_flag_list "cannonlake")
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_skylake_avx512()
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list(APPEND _available_vector_units_list "avx512ifma" "avx512vbmi")
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endmacro()
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macro(_knightslanding)
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list(APPEND _march_flag_list "knl")
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_broadwell()
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list(APPEND _available_vector_units_list "avx512f" "avx512pf" "avx512er" "avx512cd")
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endmacro()
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if(TARGET_ARCHITECTURE STREQUAL "core")
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list(APPEND _march_flag_list "core2")
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list(APPEND _available_vector_units_list "sse" "sse2" "sse3")
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@ -188,38 +274,26 @@ macro(OptimizeForArchitecture)
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else()
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message(STATUS "SSE4.1: disabled (auto-detected from this computer's CPU flags)")
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endif()
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elseif(TARGET_ARCHITECTURE STREQUAL "nehalem")
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list(APPEND _march_flag_list "nehalem")
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list(APPEND _march_flag_list "corei7")
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list(APPEND _march_flag_list "core2")
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list(APPEND _available_vector_units_list "sse" "sse2" "sse3" "ssse3" "sse4.1" "sse4.2")
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elseif(TARGET_ARCHITECTURE STREQUAL "westmere")
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list(APPEND _march_flag_list "westmere")
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list(APPEND _march_flag_list "corei7")
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list(APPEND _march_flag_list "core2")
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list(APPEND _available_vector_units_list "sse" "sse2" "sse3" "ssse3" "sse4.1" "sse4.2")
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elseif(TARGET_ARCHITECTURE STREQUAL "haswell")
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list(APPEND _march_flag_list "core-avx2")
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list(APPEND _march_flag_list "core-avx-i")
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list(APPEND _march_flag_list "corei7-avx")
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list(APPEND _march_flag_list "core2")
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list(APPEND _available_vector_units_list "sse" "sse2" "sse3" "ssse3" "sse4.1" "sse4.2" "avx" "avx2" "rdrnd" "f16c" "fma")
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elseif(TARGET_ARCHITECTURE STREQUAL "knl")
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_knightslanding()
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elseif(TARGET_ARCHITECTURE STREQUAL "cannonlake")
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_cannonlake()
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elseif(TARGET_ARCHITECTURE STREQUAL "skylake-xeon" OR TARGET_ARCHITECTURE STREQUAL "skylake-avx512")
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_skylake_avx512()
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elseif(TARGET_ARCHITECTURE STREQUAL "skylake")
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_skylake()
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elseif(TARGET_ARCHITECTURE STREQUAL "broadwell")
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list(APPEND _march_flag_list "core-avx2")
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list(APPEND _march_flag_list "core-avx-i")
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list(APPEND _march_flag_list "corei7-avx")
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list(APPEND _march_flag_list "core2")
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list(APPEND _available_vector_units_list "sse" "sse2" "sse3" "ssse3" "sse4.1" "sse4.2" "avx" "avx2" "rdrnd" "f16c" "fma")
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_broadwell()
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elseif(TARGET_ARCHITECTURE STREQUAL "haswell")
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_haswell()
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elseif(TARGET_ARCHITECTURE STREQUAL "ivy-bridge")
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list(APPEND _march_flag_list "core-avx-i")
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list(APPEND _march_flag_list "corei7-avx")
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list(APPEND _march_flag_list "core2")
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list(APPEND _available_vector_units_list "sse" "sse2" "sse3" "ssse3" "sse4.1" "sse4.2" "avx" "rdrnd" "f16c")
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_ivybridge()
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elseif(TARGET_ARCHITECTURE STREQUAL "sandy-bridge")
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list(APPEND _march_flag_list "sandybridge")
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list(APPEND _march_flag_list "corei7-avx")
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list(APPEND _march_flag_list "core2")
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list(APPEND _available_vector_units_list "sse" "sse2" "sse3" "ssse3" "sse4.1" "sse4.2" "avx")
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_sandybridge()
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elseif(TARGET_ARCHITECTURE STREQUAL "westmere")
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_westmere()
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elseif(TARGET_ARCHITECTURE STREQUAL "nehalem")
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_nehalem()
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elseif(TARGET_ARCHITECTURE STREQUAL "atom")
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list(APPEND _march_flag_list "atom")
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list(APPEND _march_flag_list "core2")
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@ -280,113 +354,84 @@ macro(OptimizeForArchitecture)
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if(NOT TARGET_ARCHITECTURE STREQUAL "none")
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set(_disable_vector_unit_list)
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set(_enable_vector_unit_list)
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_my_find(_available_vector_units_list "sse2" SSE2_FOUND)
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_my_find(_available_vector_units_list "sse3" SSE3_FOUND)
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_my_find(_available_vector_units_list "ssse3" SSSE3_FOUND)
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_my_find(_available_vector_units_list "sse4.1" SSE4_1_FOUND)
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_my_find(_available_vector_units_list "sse4.2" SSE4_2_FOUND)
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_my_find(_available_vector_units_list "sse4a" SSE4a_FOUND)
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if(DEFINED Vc_AVX_INTRINSICS_BROKEN AND Vc_AVX_INTRINSICS_BROKEN)
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UserWarning("AVX disabled per default because of old/broken compiler")
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set(AVX_FOUND false)
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set(XOP_FOUND false)
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set(FMA4_FOUND false)
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set(AVX2_FOUND false)
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UserWarning("AVX disabled per default because of old/broken toolchain")
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set(_avx_broken true)
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set(_avx2_broken true)
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set(_fma4_broken true)
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set(_xop_broken true)
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else()
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_my_find(_available_vector_units_list "avx" AVX_FOUND)
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set(_avx_broken false)
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if(DEFINED Vc_FMA4_INTRINSICS_BROKEN AND Vc_FMA4_INTRINSICS_BROKEN)
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UserWarning("FMA4 disabled per default because of old/broken compiler")
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set(FMA4_FOUND false)
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UserWarning("FMA4 disabled per default because of old/broken toolchain")
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set(_fma4_broken true)
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else()
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_my_find(_available_vector_units_list "fma4" FMA4_FOUND)
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set(_fma4_broken false)
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endif()
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if(DEFINED Vc_XOP_INTRINSICS_BROKEN AND Vc_XOP_INTRINSICS_BROKEN)
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UserWarning("XOP disabled per default because of old/broken compiler")
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set(XOP_FOUND false)
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UserWarning("XOP disabled per default because of old/broken toolchain")
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set(_xop_broken true)
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else()
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_my_find(_available_vector_units_list "xop" XOP_FOUND)
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set(_xop_broken false)
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endif()
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if(DEFINED Vc_AVX2_INTRINSICS_BROKEN AND Vc_AVX2_INTRINSICS_BROKEN)
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UserWarning("AVX2 disabled per default because of old/broken compiler")
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set(AVX2_FOUND false)
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UserWarning("AVX2 disabled per default because of old/broken toolchain")
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set(_avx2_broken true)
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else()
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_my_find(_available_vector_units_list "avx2" AVX2_FOUND)
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set(_avx2_broken false)
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endif()
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endif()
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set(USE_SSE2 ${SSE2_FOUND} CACHE BOOL "Use SSE2. If SSE2 instructions are not enabled the SSE implementation will be disabled." ${_force})
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set(USE_SSE3 ${SSE3_FOUND} CACHE BOOL "Use SSE3. If SSE3 instructions are not enabled they will be emulated." ${_force})
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set(USE_SSSE3 ${SSSE3_FOUND} CACHE BOOL "Use SSSE3. If SSSE3 instructions are not enabled they will be emulated." ${_force})
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set(USE_SSE4_1 ${SSE4_1_FOUND} CACHE BOOL "Use SSE4.1. If SSE4.1 instructions are not enabled they will be emulated." ${_force})
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set(USE_SSE4_2 ${SSE4_2_FOUND} CACHE BOOL "Use SSE4.2. If SSE4.2 instructions are not enabled they will be emulated." ${_force})
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set(USE_SSE4a ${SSE4a_FOUND} CACHE BOOL "Use SSE4a. If SSE4a instructions are not enabled they will be emulated." ${_force})
|
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set(USE_AVX ${AVX_FOUND} CACHE BOOL "Use AVX. This will double some of the vector sizes relative to SSE." ${_force})
|
||||
set(USE_AVX2 ${AVX2_FOUND} CACHE BOOL "Use AVX2. This will double all of the vector sizes relative to SSE." ${_force})
|
||||
set(USE_XOP ${XOP_FOUND} CACHE BOOL "Use XOP." ${_force})
|
||||
set(USE_FMA4 ${FMA4_FOUND} CACHE BOOL "Use FMA4." ${_force})
|
||||
mark_as_advanced(USE_SSE2 USE_SSE3 USE_SSSE3 USE_SSE4_1 USE_SSE4_2 USE_SSE4a USE_AVX USE_AVX2 USE_XOP USE_FMA4)
|
||||
if(USE_SSE2)
|
||||
list(APPEND _enable_vector_unit_list "sse2")
|
||||
else(USE_SSE2)
|
||||
list(APPEND _disable_vector_unit_list "sse2")
|
||||
endif(USE_SSE2)
|
||||
if(USE_SSE3)
|
||||
list(APPEND _enable_vector_unit_list "sse3")
|
||||
else(USE_SSE3)
|
||||
list(APPEND _disable_vector_unit_list "sse3")
|
||||
endif(USE_SSE3)
|
||||
if(USE_SSSE3)
|
||||
list(APPEND _enable_vector_unit_list "ssse3")
|
||||
else(USE_SSSE3)
|
||||
list(APPEND _disable_vector_unit_list "ssse3")
|
||||
endif(USE_SSSE3)
|
||||
if(USE_SSE4_1)
|
||||
list(APPEND _enable_vector_unit_list "sse4.1")
|
||||
else(USE_SSE4_1)
|
||||
list(APPEND _disable_vector_unit_list "sse4.1")
|
||||
endif(USE_SSE4_1)
|
||||
if(USE_SSE4_2)
|
||||
list(APPEND _enable_vector_unit_list "sse4.2")
|
||||
else(USE_SSE4_2)
|
||||
list(APPEND _disable_vector_unit_list "sse4.2")
|
||||
endif(USE_SSE4_2)
|
||||
if(USE_SSE4a)
|
||||
list(APPEND _enable_vector_unit_list "sse4a")
|
||||
else(USE_SSE4a)
|
||||
list(APPEND _disable_vector_unit_list "sse4a")
|
||||
endif(USE_SSE4a)
|
||||
if(USE_AVX)
|
||||
list(APPEND _enable_vector_unit_list "avx")
|
||||
# we want SSE intrinsics to result in instructions using the VEX prefix.
|
||||
# Otherwise integer ops (which require the older SSE intrinsics) would
|
||||
# always have a large penalty.
|
||||
list(APPEND _enable_vector_unit_list "sse2avx")
|
||||
else(USE_AVX)
|
||||
list(APPEND _disable_vector_unit_list "avx")
|
||||
endif(USE_AVX)
|
||||
if(USE_XOP)
|
||||
list(APPEND _enable_vector_unit_list "xop")
|
||||
else()
|
||||
list(APPEND _disable_vector_unit_list "xop")
|
||||
endif()
|
||||
if(USE_FMA4)
|
||||
list(APPEND _enable_vector_unit_list "fma4")
|
||||
else()
|
||||
list(APPEND _disable_vector_unit_list "fma4")
|
||||
endif()
|
||||
if(USE_AVX2)
|
||||
list(APPEND _enable_vector_unit_list "avx2")
|
||||
else()
|
||||
list(APPEND _disable_vector_unit_list "avx2")
|
||||
endif()
|
||||
|
||||
macro(_enable_or_disable _name _flag _documentation _broken)
|
||||
if(_broken)
|
||||
set(_found false)
|
||||
else()
|
||||
_my_find(_available_vector_units_list "${_flag}" _found)
|
||||
endif()
|
||||
set(USE_${_name} ${_found} CACHE BOOL "${documentation}" ${_force})
|
||||
mark_as_advanced(USE_${_name})
|
||||
if(USE_${_name})
|
||||
list(APPEND _enable_vector_unit_list "${_flag}")
|
||||
else()
|
||||
list(APPEND _disable_vector_unit_list "${_flag}")
|
||||
endif()
|
||||
endmacro()
|
||||
_enable_or_disable(SSE2 "sse2" "Use SSE2. If SSE2 instructions are not enabled the SSE implementation will be disabled." false)
|
||||
_enable_or_disable(SSE3 "sse3" "Use SSE3. If SSE3 instructions are not enabled they will be emulated." false)
|
||||
_enable_or_disable(SSSE3 "ssse3" "Use SSSE3. If SSSE3 instructions are not enabled they will be emulated." false)
|
||||
_enable_or_disable(SSE4_1 "sse4.1" "Use SSE4.1. If SSE4.1 instructions are not enabled they will be emulated." false)
|
||||
_enable_or_disable(SSE4_2 "sse4.2" "Use SSE4.2. If SSE4.2 instructions are not enabled they will be emulated." false)
|
||||
_enable_or_disable(SSE4a "sse4a" "Use SSE4a. If SSE4a instructions are not enabled they will be emulated." false)
|
||||
_enable_or_disable(AVX "avx" "Use AVX. This will all floating-point vector sizes relative to SSE." _avx_broken)
|
||||
_enable_or_disable(FMA "fma" "Use FMA." _avx_broken)
|
||||
_enable_or_disable(BMI2 "bmi2" "Use BMI2." _avx_broken)
|
||||
_enable_or_disable(AVX2 "avx2" "Use AVX2. This will double all of the vector sizes relative to SSE." _avx2_broken)
|
||||
_enable_or_disable(XOP "xop" "Use XOP." _xop_broken)
|
||||
_enable_or_disable(FMA4 "fma4" "Use FMA4." _fma4_broken)
|
||||
_enable_or_disable(AVX512F "avx512f" "Use AVX512F. This will double all floating-point vector sizes relative to AVX2." false)
|
||||
_enable_or_disable(AVX512VL "avx512vl" "Use AVX512VL. This enables 128- and 256-bit vector length instructions with EVEX coding (improved write-masking & more vector registers)." _avx2_broken)
|
||||
_enable_or_disable(AVX512PF "avx512pf" "Use AVX512PF. This enables prefetch instructions for gathers and scatters." false)
|
||||
_enable_or_disable(AVX512ER "avx512er" "Use AVX512ER. This enables exponential and reciprocal instructions." false)
|
||||
_enable_or_disable(AVX512CD "avx512cd" "Use AVX512CD." false)
|
||||
_enable_or_disable(AVX512DQ "avx512dq" "Use AVX512DQ." false)
|
||||
_enable_or_disable(AVX512BW "avx512bw" "Use AVX512BW." false)
|
||||
_enable_or_disable(AVX512IFMA "avx512ifma" "Use AVX512IFMA." false)
|
||||
_enable_or_disable(AVX512VBMI "avx512vbmi" "Use AVX512VBMI." false)
|
||||
|
||||
if(MSVC)
|
||||
# MSVC on 32 bit can select /arch:SSE2 (since 2010 also /arch:AVX)
|
||||
# MSVC on 64 bit cannot select anything (should have changed with MSVC 2010)
|
||||
_my_find(_enable_vector_unit_list "avx" _avx)
|
||||
set(_avx_flag FALSE)
|
||||
if(_avx)
|
||||
AddCompilerFlag("/arch:AVX" CXX_FLAGS Vc_ARCHITECTURE_FLAGS CXX_RESULT _avx_flag)
|
||||
_my_find(_enable_vector_unit_list "avx2" _found)
|
||||
if(_found)
|
||||
AddCompilerFlag("/arch:AVX2" CXX_FLAGS Vc_ARCHITECTURE_FLAGS CXX_RESULT _found)
|
||||
endif()
|
||||
if(NOT _avx_flag)
|
||||
if(NOT _found)
|
||||
_my_find(_enable_vector_unit_list "avx" _found)
|
||||
if(_found)
|
||||
AddCompilerFlag("/arch:AVX" CXX_FLAGS Vc_ARCHITECTURE_FLAGS CXX_RESULT _found)
|
||||
endif()
|
||||
endif()
|
||||
if(NOT _found)
|
||||
_my_find(_enable_vector_unit_list "sse2" _found)
|
||||
if(_found)
|
||||
AddCompilerFlag("/arch:SSE2" CXX_FLAGS Vc_ARCHITECTURE_FLAGS)
|
||||
|
|
@ -404,7 +449,7 @@ macro(OptimizeForArchitecture)
|
|||
else(_found)
|
||||
_my_find(_available_vector_units_list "f16c" _found)
|
||||
if(_found)
|
||||
AddCompilerFlag("-march=native" CXX_FLAGS Vc_ARCHITECTURE_FLAGS)
|
||||
AddCompilerFlag("-xCORE-AVX-I" CXX_FLAGS Vc_ARCHITECTURE_FLAGS)
|
||||
else(_found)
|
||||
_my_find(_available_vector_units_list "avx" _found)
|
||||
if(_found)
|
||||
|
|
@ -454,7 +499,7 @@ macro(OptimizeForArchitecture)
|
|||
endif(_good)
|
||||
endforeach(_flag)
|
||||
foreach(_flag ${_enable_vector_unit_list})
|
||||
AddCompilerFlag("-m${_flag}" CXX_RESULT _result CXX_FLAGS Vc_ARCHITECTURE_FLAGS)
|
||||
AddCompilerFlag("-m${_flag}" CXX_RESULT _result)
|
||||
if(_result)
|
||||
set(_header FALSE)
|
||||
if(_flag STREQUAL "sse3")
|
||||
|
|
@ -479,7 +524,7 @@ macro(OptimizeForArchitecture)
|
|||
set(_resultVar "HAVE_${_header}")
|
||||
string(REPLACE "." "_" _resultVar "${_resultVar}")
|
||||
if(_header)
|
||||
CHECK_INCLUDE_FILE("${_header}" ${_resultVar} "-m${_flag}")
|
||||
CHECK_INCLUDE_FILE_CXX("${_header}" ${_resultVar} "-m${_flag}")
|
||||
if(NOT ${_resultVar})
|
||||
set(_useVar "USE_${_flag}")
|
||||
string(TOUPPER "${_useVar}" _useVar)
|
||||
|
|
@ -490,7 +535,7 @@ macro(OptimizeForArchitecture)
|
|||
endif()
|
||||
endif()
|
||||
if(NOT _header OR ${_resultVar})
|
||||
set(Vc_ARCHITECTURE_FLAGS "${Vc_ARCHITECTURE_FLAGS} -m${_flag}")
|
||||
list(APPEND Vc_ARCHITECTURE_FLAGS "-m${_flag}")
|
||||
endif()
|
||||
endif()
|
||||
endforeach(_flag)
|
||||
|
|
|
|||
Loading…
Reference in New Issue